It is well known that MOS devices build up trapped positive charges in the oxide and interface states at Si/SiO.sub.2 interface, when exposed to ionizing radiation. These effects will induce threshold/flat band voltage shifts and the reduction of transconductance and, as a consequence, degrade the performance of devices and/or circuits. These effects are discussed in C. T. Sah, "Origin of Interface States and Oxide Charges Generated by Ionizing Radiation," IEEE Transactions on Nuclear Science, NS-23, No. 6, 1563-1568 (1976) and F. B. Mclean, "A Framework for Understanding Radiation-Induced Interface States in SiO.sub.2 MOS Structures," IEEE Transactions on Nuclear Science, NS-27, No. 6, 1651-1657 (1980). For example, the p-type substrate of N-channel MOSFET will be inverted to n-type because of the accumulation of trapped positive charges and interface states found in the gate oxide (or other insulator) so that, even without gate bias, these devices have large subthreshold leakage current. It is also expected that an apparent standby current will appear at non-operational states and that circuit function will fail during normal operation cycles with such circuits.
Generally MOS devices with thick gate oxide layers have larger degradation level. In the conventional CMOS process, the electrical isolation between devices is achieved by LOCOS field oxide, as shown in FIG. 1. The source/drain regions of neighboring devices and field oxide between them therefore form a parasitic MOSFET, which has a thick equivalent gate oxide. The threshold voltage shift induced by irradiation is so substantial that a leakage path underneath the LOCOS region may appear. Many approaches have been developed to solve these problems:
Firstly, guard rings are added as shown in FIG. 2. This approach, however, is not practical for high packing density because of the waste of chip area. Also, the coupling capacitance to the gate region is too large, which usually reduces the speed of operation. J. E. Schroeder et al., "An Advanced, Radiation Hardened Bulk CMOS/LSI Technology, IEEE Transactions on Nuclear Science, NS-28, No. 6, 4033-4037 (1981).
Secondly, a closed structure is designed as shown in FIG. 3. Here the drain region is surrounded by gate region to cut off the leakage path. This construct still has low packing density and large coupling capacitance between the gate and the drain. Again, the speed of operation is reduced.
Thirdly, the conventional LOCOS process is replaced by another process. Unfortunately, these alternatives are still developmental and have not achieved commercial application (K. Kasama et al. "A Radiation-Hard Insulator for MOS LSI Device Isolation,", IEEE Transactions on Nuclear Science, NS-32, No. 6, 3965-3970 (1985)).